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Plasma - most MIPS I(TM) opcodes: Overview
Description
The Plasma CPU core supports all MIPS I(TM) user mode instructions with only two exceptions. Unaligned load and store operations are not supported (since they are patented). Exception are also not supported. Both of these limitations can be easily avoided (see "Avoiding Limitations" below). Interrupts are supported. This "clean room" CPU core is implemented in VHDL with a three-stage pipeline. Tested on a Xilinx FPGA running at 25 MHz and an Altera FPGA running at 16.5 MHz (synthesized for 29.8 MHz).
Disclaimer
MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.
Success Stories
The Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server on a Xilinx FPGA.
 
The Plasma RISC CPU was also successfully used to control four communication robots using Xilinx Virtex FPGAs.
Block diagram
Example Instruction
The CPU is implemented with a three or four stage pipeline with an addition stage for memory read and writes. (Using the four stage pipeline enables "pipeline.vhd" which delays some control signals into the next stage.) An ADD instruction would take the following steps:
Stage #1:
1. The "pc_next" entity passes the program counter (PC) to the "mem_ctrl" entity which fetches the opcode from memory.
Stage #2:
2. The memory returns the opcode.
Stage #3:
3. "Mem_ctrl" passes the opcode to the "control" entity.
4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
5. Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".
6. Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
Stage #4 (part of stage #3 if using three stage pipeline):
7. Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
8. Based on the c_source control signals, "bus_bux" multiplexes c_bus onto reg_dest.
9. Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.
Stage #5 (part of stage #4 if using three stage pipeline):
10. Read or write memory if needed.
Supporting Documentation
The implementation is based on information found in: - "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
- "The Designer's Guide to VHDL" by Peter J. Ashenden
In addition, the MIPS I(TM) instruction set can be found by going to the MIPS Technologies, Inc. Web site (http://www.mips.com/) and then following the links to "Documentation", "Architecture Programming Publications for MIPS32(TM)", and "MIPS32(TM) Architecture for Programmers Volume II: The MIPS32(TM) Instruction Set".
Tools
The MIPS(tm) GCC ELF compiler for Windows (2.4MB) gccmips_elf.zip.
Plasma Version 3 Features
The Plasma Version 3 core now contains a bidirection serial port, interrupt controller, and hardware timer. There is C and assembly code for the Plasma Real-Time Operating System -- a fully pre-emptive RTOS supporting threads, semaphores, mutexes, message queues, timers, heaps, an interrupt manager, ANSI C library, single precision floating point library, TCP/IP protocol stack, and Web server.
Synthesis
The CPU core was synthesized for the Xilinx Spartan-3 Starter Kit Board with an Xilinx XC3S300 Spartan-3 FPGA, and an Altera EP20K200EFC484-2X FPGA.
List of Files
| FILE | PURPOSE (Directory: vhdl) | | code.txt | Input opcodes for the test bench -- test.exe "converted" | | mlite_pack.vhd | Constants and Functions Package | | tbench.vhd | Test Bench that uses plasma.vhd | | plasma_if.vhd | Top level interface to Xilinx or Altera FPGA | | -plasma.vhd | CPU core with RAM and UART | | --ram.vhd | Internal RAM for Altera FPGA | | --ram_xilinx.vhd | Internal RAM for Xilinx FPGA | | --uart.vhd | UART (can pause CPU if needed) | | --mlite_cpu.vhd | Top Level VHDL for CPU core | | ---alu.vhd | Arithmetic Logic Unit | | ---bus_mux.vhd | BUS Multiplex Unit | | ---control.vhd | Opcode Decoder | | ---mem_ctrl.vhd | Memory Controller | | ---mult.vhd | Multiplication and Division Unit | | ---pc_next.vhd | Program Counter Unit | | ---reg_bank.vhd | Register Bank for 32, 32-bit Registers | | ---shifter.vhd | Shifter Unit |
| FILE | PURPOSE (Directory: tools) | | makefile | Makefile for the PC for creating "code.txt" | | plasma.h | Plasma header file for register addresses | | boot.asm | Initializes $gp and $sp, clears .bss | | opcodes.asm | Tests all the MIPS I(tm) opcodes | | convert.c | Converts test.exe to code.txt | | ram_image.c | Creates Xilinx RAM file ram_image.vhd from ram_xilinx.vhd and code.txt | | bootldr.c | Serial port boot loader that can download another program | | mlite.c | Simulates the CPU in software | | bintohex.c | Converts test.exe to code[0-3].hex for lpm_ram | | test.c | Test program (opcodes) for the CPU core | | pi.c | Calculates the first 16 digits of PI | | count.c | Test program that counts using words | | cpu.gif | Block Diagram |
| FILE | PURPOSE (Directory: kernel) | | makefile | Makefile for Plasma RTOS | | rtos.h | Header file for Plasma RTOS | | rtos.c | Plasma pre-emptive Real-Time Operating System | | libc.c | ANSI C library subset | | math.c | Single precision floating point library | | uart.c | Serial port driver | | rtos_test.c | Test the RTOS functions | | tcpip.c | TCP/IP protocol stack | | tcpip.h | TCP/IP header file | | http.c | Web server |
Downloads
The Opencores CVSGet web page can create the 84KB mlite.tar.gz file containing all the latest code. It will ask for your name and contact information. Be sure to save the file as "mlite.tar.gz". The latest version of code can also be acquired from the CVS server cvs.opencores.org from the mlite directory.
Big/Little Endian
The CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.
Bus Interface
All signals are active high. Here are the signals for writing a character to address 0xffff when using a three stage pipeline:
entity mlite_cpu is
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
mem_address : out std_logic_vector(31 downto 0);
mem_data_w : out std_logic_vector(31 downto 0);
mem_data_r : in std_logic_vector(31 downto 0);
mem_byte_we : out std_logic_vector(3 downto 0);
mem_pause : in std_logic);
end; --entity mlite_cpu
Program:
addr value opcode
=============================
3c: 00000000 nop
40: 34040041 li $a0,0x41
44: 3405ffff li $a1,0xffff
48: a0a40000 sb $a0,0($a1)
4c: 00000000 nop
50: 00000000 nop
intr_in mem_pause
reset_in mem_byte_we Stages
ns mem_address mem_data_w mem_data_r 40 44 48 4c 50
3500 0 0 00000040 00000000 00000000 0 0 1
3600 0 0 00000044 00000000 34040041 0 0 2 1
3700 0 0 00000048 00000000 3405FFFF 0 0 3 2 1
3800 0 0 0000004C 00000000 A0A40000 0 0 3 2 1
3900 0 0 0000FFFC 41414141 00000000 1 0 3 2
4000 0 0 00000050 41414141 XXXXXX41 0 0 4 3 1
4100 0 0 00000054 00000000 00000000 0 0 2
Avoiding Limitations
This section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they are patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. Most RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. The second main limitation of the Plasma CPU is that exceptions are not supported. The main uses for exceptions are software interrupts for debugger support and calling operating system calls. Instead of using exceptions to make OS calls, call the OS functions directly.
Question and Answer
Q&A
Status
- All MIPS I(TM) instructions are implemented and tested with the following limitations (exceptions are not supported; all 32-bit memory accesses must be long word aligned since unaligned load and store operations are not supported since they are patented).
- Currently running on an Altera EP20K200EFC484-2X FPGA and a Xilinx XC3S200 FPGA.
- See "opcodes.asm" for regression test.
- Supports Interrupts.
- Includes several C test programs: Calculating PI; Prime Numbers; Showing Numbers Using Words; the Plasma RTOS; and single precision floating point library.
Legal Notice
MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc. If you use this core you are responsible for all legal issues. Free for commercial and non-commercial use as long as the author and warning notices are maintained. This software is provided by Steve Rhoads "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.
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