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OPENCORES news
| Technologic Systems TS-7300 FPGA computer support
by Jesse Off on 13-Jun-2006 |
A Quartus II project for the Technologic Systems TS-7300 FPGA Linux 2.4 computer board has been completed. The project includes support for demultiplexing the CPU to FPGA bus into a regular WISHBONE bus and also includes a reference implementation of the open ethernet core.
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| OpenTech 1.6.0 Announcement
by Jamil Khatib on 18-Apr-2006 |
* OpenTech 1.6.0 (the 12th release in 6 years) is ready with 7 CDs with design tools and open source hardware designs besides the OpenCores projects
* Extra Partners joined the OpenSupport program to support OpenTech users such as GreenSoc.com
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| OpenCores server upgrade
by Damjan Lampret on 13-Apr-2006 |
OpenCores server has been upgraded. The result of this is a much faster site, in average improving performance by twice. Also no more server restarts will be required improving accessability of the site.
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| Usbhostslave Development Kit
by Steve Fielding on 26-Mar-2006 |
Usbhostslave, the Opencores USB 1.1 host and function core, now has a complete development kit.
The kit consists of a Santa Cruz format daughter card that supports development kits from Altera, Microtronix, and others, along with pre-built hardware reference designs and full uCLinux support. http://www.base2designs.com/DUSB-PHY.htm
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Discussions (cores)
Using AES and AVR together by FpgaengineerfrankfurtREMOVE at on Sat Aug 5 01:
What in detail is the problem?
The AES will be "triggerd" or let's say fed by software you will have to
provide to the AVR. You will have to set up a memory block containing
your Software. Do you want to integrate custom software into to AVR?
Jürgen
.
read more...
About the des3 by Nwpu_zhfeng at on Wed Aug 2 20:
----- Original Message -----
From: Mark McDougall<markm at v...>
To:
Date: Wed Aug 2 02:45:05 CEST 2006
> I find it easier to build a wishbone interface - only because I'm
> more
> familair with it and it maps pretty much one-to-one to avalon.
> You'll
> need to define.
read more...
About the des3 by Nwpu_zhfeng at on Tue Aug 1 15:
dear all,
I download the des3 ip core form the opencore ,now I want to
connect it to the altea nios2, but the nios2 is 32bit cpu,so it must be
add the avalon interface between the nios2 and the DES3,could anyone
help me! thanks
my email:nwpu_zhfeng@!26.com
.
read more...
General hardware news
| OpenSoc releases Open Source SystemC to Verilog translator
by Javier Castillo Villar on 04-Oct-2004 |
OpenSoc Design has released its SystemC to Verilog Synthesizable Subset translator under a GPL license. To download it please visit OpenSoc
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| Succes story
by Boris Mlinar on 17-Mar-2004 |
The Plasma CPU core has been successfully used within a project at the University of Paderborn in Germany. The System & Circuit Technology research group has build a FPGA-based communication system for the minirobot Khepera. In this system, the Plasma CPU core executes the network protocols. Read more here.
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| 8051 and 6805 verilog source code available for free download
by Jerry D. Harthcock on 11-Nov-2003 |
QuickCores is pleased to announce that it has posted developmental versions of its Q8051 and Q6805 microcontroller CPU soft cores for free downloading and may be used without restriction. Also included is a recently enhanced JTAG debug module. Visit http://www.quickcores.com
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